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ftg for mobile via? pl 133t and ple133t chipsets cy28317-2 rev 1.0, november 25, 2006 page 1 of 20 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com 1cy28317-2 features ? single-chip system frequency synthesizer for mobile via pl133t and ple133t chipsets ? programmable clock output frequency with less than 1 mhz increment ? integrated fail-safe watchdog timer for system recovery ? automatic switch to hw-selected or sw-programmed clock frequency when watchdog timer time-out occurs ? system reset generation ca pability after a watchdog timer time-out occurs or a change in output frequency via smbus interface ? support smbus byte read/write and block read/ write operations to simplify system bios development ? vendor id and revision id support ? programmable drive strength for sdram and pci output clocks ? programmable output skew for cpu, pci and sdram ? maximized emi suppression using cypress?s spread spectrum technology ? available in 48-pin ssop and tssop packages key specifications cpu to cpu output skew: ......................................... 175 ps pci to pci output skew: ............................................ 500 ps block diagram pin configuration note: 1. signals marked with ?*? have internal pull-up resistors. [1] vdd_ref ref0 pci0_f/fs4* xtal pll ref freq pll 1 x2 x1 ref1/fs2* vdd_pci pci2:6 48mhz/fs0* 24_48mhz/fs1* pll2 2,3,4 osc vtt_pwrgd# vdd_48mhz smbus sdata logic sclk sdram0:6 sdramin 7 vdd_sdram pci1/fs3* cpu0:1, cput, cpuc 2 gnd_cpu *fs2/ref1 ref0 vtt_pwrgd# vdd_ref gnd_ref x1 x2 vdd_pci *fs4/pci0_f *fs3/pci1 gnd_pci pci2 pci3 pci4 pci5 pci6 sdramin *cpu_stop# *pci_stop# *pd# *mult_sel gnd_48mhz sdata cy28317-2 cpu0 cpu1 vdd_cpu_2.5 vdd_cpu_3.3 cput cpuc gnd_cpu rst# iref sdram6 gnd_sdram sdram0 sdram1 vdd_sdram sdram2 sdram3 gnd_sdram sdram4 sdram5 vdd_sdram vdd_48mhz 48mhz/fs0* 24_48mhz/fs1* sclk 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 logic reset rst# iref mult_sel pci_stop# cpu_stop# pd#
cy28317-2 rev 1.0, november 25, 2006 page 2 of 20 pin definitions pin name pin no. pin type pin description cpu0, cpu1 48, 47 o cpu clock output 0 through 1: cpu clocks for processor and chipset. cput, cpuc 44, 43 o differential cp u clock output: differential cpu clocks for processor. pci2:6 13, 14, 15, 16, 17 o pci clock outputs 2 through 6: 3.3v 33-mhz pci clock outputs. frequency is set by fs0:4 inputs or through serial data interface. pci1/fs3 11 i/o fixed pci clock output/frequency select 3: 3.3v pci clock outputs. as an output, the frequency is set by fs0:4 inputs or through serial data interface. this pin also serves as a power-on strap option to determine device operating frequency, as described in table 6 . pci0_f/fs4 10 i/o fixed pci clock output/frequency select 4: 3.3v free-running pci clock outputs. this pin also serves as a power-on strap option to determine device operating frequency as described in table 6 . rst# 41 o (open-drai n) reset# output: open drain system reset output. 48mhz/fs0 27 i/o 48 mhz output/frequency select 0: 3.3v 48-mhz non-spread spectrum output. this pin also serves as a po wer-on strap option to determine device operating frequency as described in table 6 . 24_48mhz/ fs1 26 i/o 24_48mhz output/frequency select 1: 3.3v 24 or 48 mhz non-spread spectrum output. this pin also serves as a power-on strap option to determine device operating frequency as described in table 6 . ref1/fs2 2 i/o reference clock output 1/frequency select 2: 3.3v 14.318 mhz output clock. this pin also serves as a power-on strap option to determine device operating frequency as described in table 6 . ref0 3 o reference clock output 0: 3.3v 14.318-mhz output clock. sdramin 18 i sdram buffer input pin: reference input for sdram buffer. sdram0:6 37, 36, 34, 33, 31, 30, 39 o sdram outputs: these thirteen dedicated outputs provide copies of the signal provided at the sdramin input. sclk 25 i clock pin for smbus circuitry. sdata 24 i/o data pin for smbus circuitry. x1 7 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 8 o crystal connection: an output connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. pd# 21 i power down control: lvttl-compatible input that places the device in power-down mode when held low. cpu_stop# 19 i cpu output control: 3.3v lvttl compatible i nput that stops cpu0, cpu1, cput, and cpuc when held low. pci_stop# 20 i pci output control: 3.3v lvttl compatible input that stop pci1:6 when held low. iref 40 i current reference input: current reference for differential cpu output. mult_sel 22 i cput and cpuc output control: control the current multiplier for differential cpu output. set this pin low for 1.0v output swing and set this pin high for 0.7v output swing. vtt_pwrgd# 4 i vtt_pwrgd#: 3.3v lvttl compatible input th at controls the fs0:4 to be latched and enables all outputs. cy28316 will sample the fs0:4 inputs and enable all clock outputs after all the vdd become valid and vtt_pwrgd# is held low.
cy28317-2 rev 1.0, november 25, 2006 page 3 of 20 vdd_ref, vdd_pci, vdd_sdram, vdd_48mhz vdd_cpu_3.3 5, 9, 28, 29, 35, 45 p power connection: power supply for core logic, pll circuitry, sdram outputs, pci outputs, reference outputs, 48-m hz output, and 24_48-mhz output. connect to 3.3v supply. vdd_cpu_2.5 46 p power connection: power supply for cpu outputs. connect to 2.5v supply. gnd_ref, gnd_pci, gnd_sdram, gnd_48mhz, gnd_cpu 1, 6, 12, 23, 32, 38, 42 g ground connections: connect all ground pins to the common system ground plane. pin definitions (continued) pin name pin no. pin type pin description table 1. swing select functions mult0 board target trace/term z reference r, iref= vdd/(3*rr) output current v oh @ z 060 rr = 221 1% iref = 5.00 ma i oh = 4*iref 1.0v @ 50 150 rr = 475 1% iref = 2.32 ma i oh = 6*iref 0.7v @ 50
cy28317-2 rev 1.0, november 25, 2006 page 4 of 20 serial data interface the cy28317-2 features a two-pi n, serial data interface that can be used to configure internal register settings that control particular device functions. data protocol the clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the controller. for block write/read operations, the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been trans- ferred. for byte/word write and byte read operations, the system controller can access i ndividual indexe d bytes. the offset of the indexed byte is encoded in the command code. the definition for the command code is defined as shown in table 2 . table 2. command code definition bit descriptions 7 0 = block read or block write operation 1 = byte/word read or byte/word write operation 6:0 byte offset for byte/word read or write operatio n. for block read or write operations, these bits need to be set at ?0000000?. table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits ?00000000? stands for block operation 11:18 command code ? 8 bits ?00000000? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge ... data byte n/slave acknowledge... 39:46 data byte from slave ? 8 bits ... data byte n ? 8 bits 47 acknowledge ... acknowledge from slave 48:55 data byte from slave ? 8 bits ... stop 56 acknowledge ... data bytes from slave/acknowledge ... data byte n from slave - 8 bits ... not acknowledge ... stop
cy28317-2 rev 1.0, november 25, 2006 page 5 of 20 table 4. word read and word write protocol word write protocol word read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte low ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte high ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38 stop 30:37 data byte low from slave ? 8 bits 38 acknowledge 39:46 data byte high from slave ? 8 bits 47 not acknowledge 48 stop table 5. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop
cy28317-2 rev 1.0, november 25, 2006 page 6 of 20 cy28317-2 serial configuration map 1. the serial bits will be read by the clock driver in the following order: byte 0 ? bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 ? bits 7, 6, 5, 4, 3, 2, 1, 0 byte n ? bits 7, 6, 5, 4, 3, 2, 1, 0 2. all unused register bits (reserved and n/a) should be written to a ?0? level. 3. all register bits labeled ?write with 1" must be written to one during initialization. byte 0: control register 0 bit pin# name default description bit 7 ? spread select1 0 see definition in bit[0] bit 6 ? sel2 0 see table 6 bit 5 ? sel1 0 see table 6 bit 4 ? sel0 0 see table 6 bit 3 ? fs_override 0 0 = select operating frequency by fs[4:0] input pins 1 = select operating frequency by sel[4:0] settings bit 2 ? sel4 0 see table 6 bit 1 ? sel3 0 see table 6 bit 0 ? spread select0 0 ?00? = off ?01? = ?0.5% ?10? = 0.5% ?11? = 0.25% byte 1: control register 1 bit pin# name default description bit 7 10 latched fs4 input x latched fs[4:0] inputs. these bits are read-only. bit 6 11 latched fs3 input x bit 5 2 latched fs2 input x bit 4 26 latched fs1 input x bit 3 27 latched fs0 input x bit 2 48 cpu0 1 (active/inactive) bit 1 47 cpu1 1 (active/inactive) bit 0 44, 43 cput, cpuc 1 (active/inactive) byte 2: control register 2 bit pin# name default description bit 7 39 sdram6 1 (active/inactive) bit 6 10 pci0_f 1 (active/inactive) bit 5 17 pci6 1 (active/inactive) bit 4 16 pci5 1 (active/inactive) bit 3 15 pci4 1 (active/inactive) bit 2 14 pci3 1 (active/inactive) bit 1 13 pci2 1 (active/inactive) bit 0 11 pci1 1 (active/inactive) byte 3: control register 3 bit pin# name default description bit 7 ? reserved 1 reserved bit 6 ? sel_48mhz 0 0 = 24 mhz 1 = 48 mhz
cy28317-2 rev 1.0, november 25, 2006 page 7 of 20 bit 5 27 48mhz 1 (active/inactive) bit 4 26 24_48mhz 1 (active/inactive) bit 3 ? reserved 1 reserved bit 2 31, 30 sdram4:5 1 (active/inactive) bit 1 34, 33 sdram2:3 1 (active/inactive) bit 0 37, 36 sdram0:1 1 (active/inactive) byte 4: control register 4 bit pin# name default description bit 7 ? reserved 0 reserved bit 6 ? reserved 0 reserved bit 5 ? reserved 0 reserved bit 4 ? reserved 0 reserved bit 3 ? reserved 0 reserved bit 2 ? reserved 0 reserved bit 1 ? reserved 0 reserved bit 0 ? reserved 0 reserved byte 3: control register 3 bit pin# name default description byte 5: control register 5 bit pin# name default description bit 7 ? reserved 0 reserved bit 6 ? reserved 0 reserved bit 5 ? reserved 0 reserved bit 4 ? cpu1 stop control 0 0 = cpu1 will be stopped when cpu_stop# is active 1 = cpu1 will not be stopped when cpu_stop# is active bit 3 ? cpu0 stop control 0 0 = cpu0 will be stopped when cpu_stop# is active 1 = cpu0 will not be stopped when cpu_stop# is active bit 2 ? cput and cpuc stop control 0 0 = cput and cpuc will be stopped when cpu_stop# is active 1 = cput and cpuc will not be stopped when cpu_stop# is active bit 1 2 ref1 1 (active/inactive) bit 0 3 ref0 1 (active/inactive) byte 6: watchdog timer register bit name default pin description bit 7 pci_skew1 0 pci skew control 00 = normal 01 = ?500 ps 10 = reserved 11 = +500 ps bit 6 pci_skew0 0
cy28317-2 rev 1.0, november 25, 2006 page 8 of 20 bit 5 wd_timer4 1 these bits store the time-out va lue of the watchdog timer. the scale of the timer is determined by the prescaler. the timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. if the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. when the watchdog timer reaches ?0,? it will set the wd_to_status bit and generate reset if rst_en_wd is enabled. bit 4 wd_timer3 1 bit 3 wd_timer2 1 bit 2 wd_timer1 1 bit 1 wd_timer0 1 bit 0 wd_pre_sc aler 0 0 = 150 ms 1 = 2.5 sec byte 6: watchdog timer register (continued) bit name default pin description byte 7: control register 7 bit pin# name default pin description bit 7 ? reserved 0 reserved bit 6 25 24_48mhz_drv 1 0 = norm, 1 = high drive bit 5 26 48mhz_drv 1 0 = norm, 1 = high drive bit 4 ? reserved 0 reserved bit 3 ? reserved 0 reserved bit 2 ? reserved 0 reserved bit 1 ? reserved 0 reserved bit 0 ? reserved 0 reserved byte 8: vendor id and revision id register (read only) bit name default pin description bit 7 revision_id3 0 revision id bit[3] bit 6 revision_id2 0 revision id bit[2] bit 5 revision_id1 0 revision id bit[1] bit 4 revision_id0 0 revision id bit[0] bit 3 vendor_id3 1 bit[3] of cypress semiconductor?s vendor id. this bit is read-only. bit 2 vendor_id2 0 bit[2] of cypress semiconductor?s vendor id. this bit is read-only. bit 1 vendor _id1 0 bit[1] of cypress semiconductor?s vendor id. this bit is read-only. bit 0 vendor _id0 0 bit[0] of cypress semiconductor?s vendor id. this bit is read-only. byte 9: system reset an d watchdog timer register bit name default pin description bit 7 sdram_drv 0 sdram clock output drive strength 0 = normal 1 = high drive bit 6 pci_drv 0 pci clock output drive strength 0 = normal 1 = high drive bit 5 reserved 0 reserved bit 4 rst_en_wd 0 this bit will enable the generation of a reset pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled
cy28317-2 rev 1.0, november 25, 2006 page 9 of 20 bit 3 rst_en_fc 0 this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled bit 2 wd_to_status 0 watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurred (read); clear wd_to_status (write) bit 1 wd_en 0 0 = stop and reload watchdog timer. unlock cy28317-2 from recovery frequency mode. 1 = enable watchdog timer. it will start counting down after a frequency change occurs. note: cy28317-2 will generate a system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a watchdog timer time-out occurs. under recovery frequency mode, cy28317-2 will not respond to any attempt to change output frequency vi a the smbus control bytes. system software can unlock cy28317-2 from its recovery frequency mode by clearing the wd_en bit. bit 0 cpu0:1_drv 0 cpu0:1 clock output drive strength 0 = normal 1 = high drive byte 9: system reset and watchdog timer register (continued) bit name default pin description byte 10: skew control register bit name default description bit 7 cpu0:1_skew2 0 cpu 0:1 output skew control 000 = normal 001 = ?150 ps 010 = ?300 ps 011 = ?450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps bit 6 cpu0:1_skew1 0 bit 5 cpu0:1_skew0 0 bit 4 reserved 0 reserved bit 3 reserved 0 reserved bit 2 reserved 0 reserved bit 1 cput&c_skew1 0 cput and cpuc output skew control 00 = normal 01 = ?150 ps 10 = +150 ps 11 = +300 ps bit 0 cput&c_skew0 0
cy28317-2 rev 1.0, november 25, 2006 page 10 of 20 byte 11: recovery frequency n-value register bit name default pin description bit 7 rocv_freq_n7 0 if rocv_fre q_sel is set, cy28317-2 will use the values programmed in rocv_freq_n[7:0] and ro cv_freq_m[6:0] to determine the recovery cpu output frequency when a watchdog timer time-out occurs. the setting of the fs_override bit determines the frequency ratio for cpu and pci. when it is cleared, cy28317-2 will use the same frequency ratio stated in the latched fs[4:0] register. when it is set, cy28317-2 will use the frequency ratio stated in the sel[4:0] register. cy28317-2 supports programmable cpu frequencies ranging from 50 mhz to 248 mhz. cy28317-2 will change the output frequen cy whenever there is an update to either rocv_freq_n[7:0] or rocv_fre q_m[6:0]. therefore, it is recom- mended to use word or block write to update both registers within the same smbus bus operation. bit 6 rocv_freq_n6 0 bit 5 rocv_freq_n5 0 bit 4 rocv_freq_n4 0 bit 3 rocv_freq_n3 0 bit 2 rocv_freq_n2 0 bit 1 rocv_freq_n1 0 bit 0 rocv_freq_n0 0 byte 12: recovery frequency m-value register bit name default pin description bit 7 rocv_freq_sel 0 rocv_ freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. the cloc k generator will automatically switch to the recovery cpu frequency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv_f req_n[7:0] and rocv_freq_m[6:0] bit 6 rocv_freq_m6 0 if rocv_freq_sel is set, cy 28317-2 will use the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] to determine the recovery cpu output frequency when a watchdog timer time-out occurs. the setting of the fs_override bit determines the frequency ratio for cpu, sdram, and pci. when it is cleared, cy28317-2 will use the same frequency ratio stated in the latched fs[4:0] regi ster. when it is set, cy28317-2 will use the frequency ratio stated in the sel[4:0] register. cy28317-2 supports programmable cpu frequencies ranging from 50 mhz to 248 mhz. cy28317-2 will change the output frequency whenever there is an update to either rocv_freq_n[7:0] or rocv_freq_m[6:0]. t herefore, it is recom- mended to use word or block write to update both registers within the same smbus bus operation. bit 5 rocv_freq_m5 0 bit 4 rocv_freq_m4 0 bit 3 rocv_freq_m3 0 bit 2 rocv_freq_m2 0 bit 1 rocv_freq_m1 0 bit 0 rocv_freq_m0 0 byte 13: programmable frequency select n-value register bit name default pin description bit 7 cpu_fsel_n7 0 if prog_freq_en is set, cy28317-2 will use the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] to determine the cpu output frequency. the new frequency will start to load whenever cpu_fselm[6:0] is updated. the setting of the fs_override bit det ermines the frequency ratio for cpu, sdram and pci. when it is cleared, cy28317-2 will use the same frequency ratio stated in the latched fs[4:0] register. when it is set, cy28317-2 will use the frequency ratio stated in the sel[4:0] register. cy28317-2 supports programmable cpu frequencies ranging from 50 mhz to 248 mhz. bit 6 cpu_fsel_n6 0 bit 5 cpu_fsel_n5 0 bit 4 cpu_fsel_n4 0 bit 3 cpu_fsel_n3 0 bit 2 cpu_fsel_n2 0 bit 1 cpu_fsel_n1 0 bit 0 cpu_fsel_n0 0
cy28317-2 rev 1.0, november 25, 2006 page 11 of 20 byte 14: programmable frequency select m-value register bit name default description bit 7 pro_freq_en 0 programmabl e output frequencies enabled 0 = disabled 1 = enabled bit 6 cpu_fsel_m6 0 if prog_freq_en is set, cy 28317-2 will use the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0 ] to determine the cpu output frequency. the new frequency will start to load whenever cpu_fselm[6:0] is updated. the setting of the fs_override bit dete rmines the frequency ratio for cpu, sdram and pci. when it is cleared, cy28317-2 will use the same frequency ratio stated in the latched fs[4:0] register . when it is set, cy28317-2 will use the frequency ratio stated in the sel[4:0] register. cy28317-2 supports programmable cpu frequencies ranging from 50 mhz to 248 mhz. bit 5 cpu_fsel_m5 0 bit 4 cpu_fsel_m4 0 bit 3 cpu_fsel_m3 0 bit 2 cpu_fsel_m2 0 bit 1 cpu_fsel_m1 0 bit 0 cpu_fsel_m0 0 byte 15: reserved register bit pin# name default description bit 7 ? reserved 0 reserved bit 6 ? reserved 0 reserved bit 5 ? reserved 0 reserved bit 4 ? reserved 0 reserved bit 3 ? reserved 0 reserved bit 2 ? vendor test mode 0 reserved. write with ?0? bit 1 ? vendor test mode 1 test mode. write with ?1? bit 0 ? vendor test mode 1 test mode. write with ?1? byte 16: reserved register bit pin# name default description bit 7 ? reserved 0 reserved bit 6 ? reserved 0 reserved bit 5 ? reserved 0 reserved bit 4 ? reserved 0 reserved bit 3 ? reserved 0 reserved bit 2 ? reserved 0 reserved bit 1 ? reserved 0 reserved byte 17: reserved register bit pin# name default description bit 7 ? reserved 0 reserved bit 6 ? reserved 0 reserved bit 5 ? reserved 0 reserved bit 4 ? reserved 0 reserved bit 3 ? reserved 0 reserved bit 2 ? reserved 0 reserved bit 1 ? reserved 0 reserved
cy28317-2 rev 1.0, november 25, 2006 page 12 of 20 table 6. additional frequency selections th rough serial data interface data bytes input conditions output frequency pll gear constant (g) fs4 fs3 fs2 fs1 fs0 cpu pci sel4 sel3 sel2 sel1 sel0 0 0 0 0 0 200.0 33.3 48.000741 0 0 0 0 1 190.0 38.0 48.000741 0 0 0 1 0 180.0 36.0 48.000741 0 0 0 1 1 170.0 34.0 48.000741 0 0 1 0 0 166.0 33.2 48.000741 0 0 1 0 1 160.0 32.0 48.000741 0 0 1 1 0 150.0 37.5 48.000741 0 0 1 1 1 145.0 36.3 48.000741 0 1 0 0 0 140.0 35.0 48.000741 0 1 0 0 1 136.0 34.0 48.000741 0 1 0 1 0 130.0 32.5 48.000741 0 1 0 1 1 124.0 31.0 48.000741 0 1 1 0 0 67.2 33.6 48.000741 0 1 1 0 1 100.8 33.6 48.000741 0 1 1 1 0 118.0 39.3 48.000741 0 1 1 1 1 134.4 33.6 48.000741 1 0 0 0 0 67.0 33.5 48.000741 1 0 0 0 1 100.5 33.5 48.000741 1 0 0 1 0 115.0 38.3 48.000741 1 0 0 1 1 134.0 33.5 48.000741 1 0 1 0 0 66.8 33.4 48.000741 1 0 1 0 1 100.2 33.4 48.000741 1 0 1 1 0 110.0 36.7 48.000741 1 0 1 1 1 133.6 33.4 48.000741 1 1 0 0 0 105.0 35.0 48.000741 1 1 0 0 1 90.0 30.0 48.000741 1 1 0 1 0 85.0 28.3 48.000741 1 1 0 1 1 78.0 39.0 48.000741 1 1 1 0 0 66.6 33.3 48.000741 1 1 1 0 1 100.0 33.3 48.000741 1 1 1 1 0 75.0 37.5 48.000741 1 1 1 1 1 133.3 33.3 48.000741
cy28317-2 rev 1.0, november 25, 2006 page 13 of 20 programmable output frequency, watchdog timer and recovery output frequency functional description the programmable output frequency feature allows users to generate any cpu output frequen cy in the range of 50 mhz to 248 mhz. cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. the watchdog timer and recovery output frequency features allow users to implement a recovery mechanism when the system hangs or gets unstable. system bios or other control software can enable the watchdog timer before they attempt to make a frequ ency change. if the system hangs and a watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. all the related registers are summarized in table 7 . table 7. register summary name description pro_freq_en programmable output frequencies enabled 0 = disabled (default) 1 = enabled when it is disabled, the operating output frequency will be determined by either the latched value of fs[4:0] inputs or the programmed value of sel[4:0]. if fs_override bit is clear, latched fs[4:0] inputs will be used. if the fs_override bit is set, t he programmed value of sel[4:0] will be used. when it is enabled, the cpu output frequency will be determined by the programmed value of cpufsel_n, cpufsel_m, and the pll gear constant. the program value of fs _override, sel[4:0] or the latched value of fs[4:0] will determine the pll gear constant and the frequency ratio between cpu and other frequency outputs fs_override when pro_freq_en is cleared or disabled, 0 = select operating frequency by fs input pins (default) 1 = select operating frequency by sel bits in smbus control bytes when pro_freq_en is set or enabled, 0 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the latched value of fs input pins (default) 1 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the programmed value of sel bits in smbus control bytes cpu_fsel_n, cpu_fsel_m when prog_freq_en is set or enabled, the va lues programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] determine the cpu output frequency. the new frequency will start to load whenever there is an update to either cpu_fsel_n[7:0] or cpu_fsel_m[6:0]. therefore, it is recommended to use word or block write to update both registers within the same smbus bus operation. the setting of fs_override bit determines the freq uency ratio for cpu and pci. when fs_override is cleared or disabled, the frequency ratio follows the latched value of the fs input pins. when fs_override is set or enabled, the frequency ratio follows the programmed value of sel bits in smbus control bytes. rocv_freq_sel rocv_freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. the clock generator will automatically swit ch to the recovery cpu frequency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv_f req_n[7:0] and rocv_freq_m[6:0] rocv_freq_n[7:0], rocv_freq_m[6:0] when rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be used to determine the recovery cp u output frequency when a watchdog timer time-out occurs the setting of the fs_override bit determines the frequency ratio for cpu and sdram. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. the new frequency will start to load whenever there is an update to either rocv_freq_n[7:0] or rocv_freq_m[6:0]. therefor e, it is recommended to use word or block write to update both registers within the same smbus bus operation. wd_en 0 = stop and reload watchdog timer. unlock cy28317-2 from recovery frequency mode. 1 = enable watchdog timer. it will start counting down after a frequency change occurs. note: cy28317-2 will generate system reset, reload a reco very frequency, and lock itself into a recovery frequency mode after a watchdog timer time-out o ccurs. under recovery frequency mode, cy28317-2 will not respond to any attempt to change output frequency via the smbus control bytes. system software can unlock cy28317-2 from its recovery frequency mode by clearing the wd_en bit. wd_to_status watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurred (read); clear wd_to_status (write)
cy28317-2 rev 1.0, november 25, 2006 page 14 of 20 how to program cpu output frequency when the programmable output frequency feature is enabled (pro_freq_en bit is set), the cpu output frequency is deter- mined by the following equation: fcpu = g * (n+3)/(m+3) ?n? and ?m? are the values programmed in programmable frequency select n-value register and m-value register, respectively. ?g? stands for the pll gear constant, which is determined by the programmed value of fs[4:0] or sel[4:0]. the value is listed in table 4 . the ratio of (n+3) and (m+3) need to be greater than ?1? [(n+3)/(m+3) > 1]. the following table lists set of n and m values for different frequency output ranges.this example uses a fixed value for the m-value register and selects the cpu output frequency by changing the value of the n-value register. wd_timer[4:0] these bits store the time-out value of the watc hdog timer. the scale of the timer is determine by the prescaler. the timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. if the prescaler is set to 2.5 sec, it can suppor t a value from 2.5 sec to 80 sec. when the watchdog timer reaches ?0,? it will set the wd_to_status bit. wd_pre_scaler 0 = 150 ms 1 = 2.5 sec rst_en_wd this bit will enable the generation of a rese t pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled rst_en_fc this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled table 7. register summary (continued) name description table 8. examples of n and m value for different cpu frequency range frequency ranges gear constants fixed value for m-value register range of n-value register for different cpu frequency 50 mhz ? 129 mhz 48.00741 93 97?255 130 mhz ? 248 mhz 48.00741 45 127?245
cy28317-2 rev 1.0, november 25, 2006 page 15 of 20 absolute maximum ratings [2] stresses greater than those listed in this table may cause perman ent damage to the device. these represent a stress rating only . operation of the device at these or any ot her conditions above those specified in th e operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. parameter descrip tion rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t b ambient temperature under bias ?55 to +125 c t a operating temperature 0 to +70 c esd prot input esd protection 2 (min.) kv dc electrical characteristics: t a = 0c to +70c, v ddq3 = 3.3v 5% [3] parameter description test condition min. typ. max. unit supply current i dd3 3.3v supply current v dd = 3.465v, fcpu = 133 mhz 250 ma i ddpd3 3.3v shut down current v dd = 3.465v 25 ma logic inputs v il input low voltage gnd ? 0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input low current [4] ?25 a i ih input high current [4] 10 a clock outputs v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ?1 ma 3.1 v i ol output low current pci0:5 v ol = 1.5v 70 110 135 ma ref0:1 v ol = 1.5v 50 70 100 ma 48 mhz v ol = 1.5v 50 70 100 ma 24 mhz v ol = 1.5v 50 70 100 ma sdram v ol = 1.5v 70 110 135 ma i oh output high current pci0:5 v oh = 1.5v 70 110 135 ma ref0:1 v oh = 1.5v 50 70 100 ma 48 mhz v oh = 1.5v 50 70 100 ma 24 mhz v oh = 1.5v 50 70 100 ma sdram v oh = 1.5v 70 110 135 ma notes: 2. the voltage on any input or i/o pin cannot exceed the power pi n during power-up. power supply sequencing is not required. 3. all clock outputs loaded with 6" 60 transmission lines with 20-pf capacitors. 4. cy28317-2 logic inputs (except fs3) have internal pull-up devices (pull-ups not full cmos level). logic input fs3 has an inte rnal pull-down device.
cy28317-2 rev 1.0, november 25, 2006 page 16 of 20 ac electrical characteristics t a = 0c to +70c, v ddq3 = 3.3v5%, f xtl = 14.31818 mhz ac clock parameters are tested and guarant eed over stated operating conditions using the stated lump capacitive load at the clock output; spread spectrum is disabled. notes: 5. x1 input threshold voltage (typical) is v dd /2. 6. the cy28317-2 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. th e total load placed on the crystal is 18 pf; this includes typical stray ca pacitance of short pcb traces to the crystal. 7. x1 input capac itance is applicable w hen driving x1 with an ex ternal clock source (x2 is left unconnected). 8. determined as a fraction of 2* (t rp ? t rn ). where t rp is a rising edge and t rn is an intersection falling edge. crystal oscillator v th x1 input threshold voltage [5] v ddq3 = 3.3v 1.65 v c load load capacitance, imposed on external crystal [6] 18 pf c in,x1 x1 input capacitance [7] pin x2 unconnected tbd pf pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6 pf l in input pin inductance 7nh dc electrical characteristics: t a = 0c to +70c, v ddq3 = 3.3v 5% [3] (continued) parameter description test condition min. typ. max. unit cpu clock outputs [8] parameter description test condition/comments cpu = 100 mhz cpu = 133 mhz unit min. typ. max. min. typ. max. t r output rise edge rate 1.0 4.0 1.0 4.0 v/ns t f output fall edge rate 1.0 2.0 1.0 2.0 v/ns t d duty cycle measured at 50% point 45 55 45 55 % t jc jitter, cycle to cycle 250 250 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance v o = v x 50 50
cy28317-2 rev 1.0, november 25, 2006 page 17 of 20 pci clock outputs, pci (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit t p period measured on the rising edge at 1.5v 30 ns t h high time duration of cl ock cycle above 2.4v 12 ns t l low time duration of cl ock cycle below 0.4v 12 ns t r output rise edge rate measur ed from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on the rising and falling edges at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on the rising edge at 1.5v. maximum difference of cycle time bet ween two adjacent cycles. 250 ps t sk output skew measured on the rising edge at 1.5v 500 ps t o cpu to pci clock skew covers all cpu/pci outputs. measured on the rising edge at 1.5v. cpu leads pci output. 1.5 4 ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value durin g switching transition. used for determining series termination value. 30 ref clock outputs (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on the rising and falling edges at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value du ring switching transition. used for determining series termination value. 40 48-mhz clock output (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual determined by pll divider ratio (see m/n below) 48.008 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on the rising and falling edges at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 40
cy28317-2 rev 1.0, november 25, 2006 page 18 of 20 24-mhz clock output (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual determined by pll divider ratio (see m/n below) 24.004 mhz f d deviation from 24 mhz (24.004 ? 24)/24 +167 ppm m/n pll ratio (14.31818 mhz x 57/34 = 24.004 mhz) 57/34 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on the rising and falling edges at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 40 ordering information ordering code package type operating range cy28317pvc-2 48-pin ssop commercial, 0c to 70c cy28317pvc-2t 48-pin ssop - tape and reel commercial, 0c to 70c cy28317zc-2 48-pin tssop commercial, 0c to 70c CY28317ZC-2T 48-pin tssop - tape and reel commercial, 0c to 70c
cy28317-2 rev 1.0, november 25, 2006 page 19 of 20 layout diagram g = via to gnd plane layer v = via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors g fb +3.3v supply c4 ceramic caps c3 = 10?22 f c4 = 0.005 f 10 f fb = dale ilb1206 - 300 (300 @ 100 mhz) or tdk acb2012l-120 0.005 f g g v ddq3 c3 c6 = 0.01 f 48 47 46 45 44 43 42 41 40 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 g v cy28317-2 g v g v g v g g g g g g g g g g g g g g g g g g v g g g fb +2.5v supply c4 10 f 0.005 f g g v ddq2 c3 g v g v g
rev 1.0, november 25, 2006 page 20 of 20 cy28317-2 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimension 48-leadshrunksmalloutlinepackageo48 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48

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